
#ifndef GMACHINE_HEADER_GPROFILE_H
#define GMACHINE_HEADER_GPROFILE_H

#include "GObjects.h"

namespace GMachine
{
	///////////////////////////////////////////////////////////////
	//	Register Name
	///////////////////////////////////////////////////////////////
	namespace Regname
	{
		template<int type, U8 id>	class DefineRegister { public:	enum { regid = id }; };
		//----------------------------------------------------
		// Integer register name
		//----------------------------------------------------
		typedef DefineRegister<0, 0>	TG0;  const TG0		G0;
		typedef DefineRegister<0, 1>	TG1;  const TG1		G1;
		typedef DefineRegister<0, 2>	TG2;  const TG2		G2;
		typedef DefineRegister<0, 3>	TG3;  const TG3		G3;
		typedef DefineRegister<0, 4>	TG4;  const TG4		G4;
		typedef DefineRegister<0, 5>	TG5;  const TG5		G5;
		typedef DefineRegister<0, 6>	TG6;  const TG6		G6;
		typedef DefineRegister<0, 7>	TG7;  const TG7		G7;
		typedef DefineRegister<0, 8>	TG8;  const TG8		G8;
		typedef DefineRegister<0, 9>	TG9;  const TG9		G9;
		typedef DefineRegister<0, 10>	TG10; const TG10	G10;
		typedef DefineRegister<0, 11>	TG11; const TG11	G11;
		typedef DefineRegister<0, 12>	TG12; const TG12	G12;
		typedef DefineRegister<0, 13>	TG13; const TG13	G13;
		typedef DefineRegister<0, 14>	TG14; const TG14	G14;
		typedef DefineRegister<0, 15>	TG15; const TG15	G15;
		typedef DefineRegister<0, 16>	TG16; const TG16	G16;
		typedef DefineRegister<0, 17>	TG17; const TG17	G17;
		typedef DefineRegister<0, 18>	TG18; const TG18	G18;
		typedef DefineRegister<0, 19>	TG19; const TG19	G19;
		typedef DefineRegister<0, 20>	TG20; const TG20	G20;
		typedef DefineRegister<0, 21>	TG21; const TG21	G21;
		typedef DefineRegister<0, 22>	TG22; const TG22	G22;
		typedef DefineRegister<0, 23>	TG23; const TG23	G23;
		typedef DefineRegister<0, 24>	TG24; const TG24	G24;
		typedef DefineRegister<0, 25>	TG25; const TG25	G25;
		typedef DefineRegister<0, 26>	TG26; const TG26	G26;
		typedef DefineRegister<0, 27>	TG27; const TG27	G27;
		typedef DefineRegister<0, 28>	TG28; const TG28	G28;
		typedef DefineRegister<0, 29>	TG29; const TG29	G29;
		typedef DefineRegister<0, 30>	TG30; const TG30	G30;
		typedef DefineRegister<0, 31>	TG31; const TG31	G31;

		//----------------------------------------------------
		// Floating register name
		//----------------------------------------------------
		typedef DefineRegister<1, 64>	TF0;  const TF0		F0;
		typedef DefineRegister<1, 65>	TF1;  const TF1		F1;
		typedef DefineRegister<1, 66>	TF2;  const TF2		F2;
		typedef DefineRegister<1, 67>	TF3;  const TF3		F3;
		typedef DefineRegister<1, 68>	TF4;  const TF4		F4;
		typedef DefineRegister<1, 69>	TF5;  const TF5		F5;
		typedef DefineRegister<1, 70>	TF6;  const TF6		F6;
		typedef DefineRegister<1, 71>	TF7;  const TF7		F7;
		typedef DefineRegister<1, 72>	TF8;  const TF8		F8;
		typedef DefineRegister<1, 73>	TF9;  const TF9		F9;
		typedef DefineRegister<1, 74>	TF10; const TF10	F10;
		typedef DefineRegister<1, 75>	TF11; const TF11	F11;
		typedef DefineRegister<1, 76>	TF12; const TF12	F12;
		typedef DefineRegister<1, 77>	TF13; const TF13	F13;
		typedef DefineRegister<1, 78>	TF14; const TF14	F14;
		typedef DefineRegister<1, 79>	TF15; const TF15	F15;
		typedef DefineRegister<1, 80>	TF16; const TF16	F16;
		typedef DefineRegister<1, 81>	TF17; const TF17	F17;
		typedef DefineRegister<1, 82>	TF18; const TF18	F18;
		typedef DefineRegister<1, 83>	TF19; const TF19	F19;
		typedef DefineRegister<1, 84>	TF20; const TF20	F20;
		typedef DefineRegister<1, 85>	TF21; const TF21	F21;
		typedef DefineRegister<1, 86>	TF22; const TF22	F22;
		typedef DefineRegister<1, 87>	TF23; const TF23	F23;
		typedef DefineRegister<1, 88>	TF24; const TF24	F24;
		typedef DefineRegister<1, 89>	TF25; const TF25	F25;
		typedef DefineRegister<1, 90>	TF26; const TF26	F26;
		typedef DefineRegister<1, 91>	TF27; const TF27	F27;
		typedef DefineRegister<1, 92>	TF28; const TF28	F28;
		typedef DefineRegister<1, 93>	TF29; const TF29	F29;
		typedef DefineRegister<1, 94>	TF30; const TF30	F30;
		typedef DefineRegister<1, 95>	TF31; const TF31	F31;

		//====================================================
		//					Notice!
		//	From 0 - 127, is instance register;
		//	From 128 - 255, is reference register.
		//====================================================

		//----------------------------------------------------
		// String register name
		//----------------------------------------------------
		typedef DefineRegister<2, 128>	TS0;  const TS0		S0;
		typedef DefineRegister<2, 129>	TS1;  const TS1		S1;
		typedef DefineRegister<2, 130>	TS2;  const TS2		S2;
		typedef DefineRegister<2, 131>	TS3;  const TS3		S3;
		typedef DefineRegister<2, 132>	TS4;  const TS4		S4;
		typedef DefineRegister<2, 133>	TS5;  const TS5		S5;
		typedef DefineRegister<2, 134>	TS6;  const TS6		S6;
		typedef DefineRegister<2, 135>	TS7;  const TS7		S7;
		typedef DefineRegister<2, 136>	TS8;  const TS8		S8;
		typedef DefineRegister<2, 137>	TS9;  const TS9		S9;
		typedef DefineRegister<2, 138>	TS10; const TS10	S10;
		typedef DefineRegister<2, 139>	TS11; const TS11	S11;
		typedef DefineRegister<2, 140>	TS12; const TS12	S12;
		typedef DefineRegister<2, 141>	TS13; const TS13	S13;
		typedef DefineRegister<2, 142>	TS14; const TS14	S14;
		typedef DefineRegister<2, 143>	TS15; const TS15	S15;
		typedef DefineRegister<2, 144>	TS16; const TS16	S16;
		typedef DefineRegister<2, 145>	TS17; const TS17	S17;
		typedef DefineRegister<2, 146>	TS18; const TS18	S18;
		typedef DefineRegister<2, 147>	TS19; const TS19	S19;
		typedef DefineRegister<2, 148>	TS20; const TS20	S20;
		typedef DefineRegister<2, 149>	TS21; const TS21	S21;
		typedef DefineRegister<2, 150>	TS22; const TS22	S22;
		typedef DefineRegister<2, 151>	TS23; const TS23	S23;
		typedef DefineRegister<2, 152>	TS24; const TS24	S24;
		typedef DefineRegister<2, 153>	TS25; const TS25	S25;
		typedef DefineRegister<2, 154>	TS26; const TS26	S26;
		typedef DefineRegister<2, 155>	TS27; const TS27	S27;
		typedef DefineRegister<2, 156>	TS28; const TS28	S28;
		typedef DefineRegister<2, 157>	TS29; const TS29	S29;
		typedef DefineRegister<2, 158>	TS30; const TS30	S30;
		typedef DefineRegister<2, 159>	TS31; const TS31	S31;

		//----------------------------------------------------
		// Handle register name
		//----------------------------------------------------
		typedef DefineRegister<3, 224>	TH0;  const TH0		H0;
		typedef DefineRegister<3, 225>	TH1;  const TH1		H1;
		typedef DefineRegister<3, 226>	TH2;  const TH2		H2;
		typedef DefineRegister<3, 227>	TH3;  const TH3		H3;
		typedef DefineRegister<3, 228>	TH4;  const TH4		H4;
		typedef DefineRegister<3, 229>	TH5;  const TH5		H5;
		typedef DefineRegister<3, 230>	TH6;  const TH6		H6;
		typedef DefineRegister<3, 231>	TH7;  const TH7		H7;
		typedef DefineRegister<3, 232>	TH8;  const TH8		H8;
		typedef DefineRegister<3, 233>	TH9;  const TH9		H9;
		typedef DefineRegister<3, 234>	TH10; const TH10	H10;
		typedef DefineRegister<3, 235>	TH11; const TH11	H11;
		typedef DefineRegister<3, 236>	TH12; const TH12	H12;
		typedef DefineRegister<3, 237>	TH13; const TH13	H13;
		typedef DefineRegister<3, 238>	TH14; const TH14	H14;
		typedef DefineRegister<3, 239>	TH15; const TH15	H15;
		typedef DefineRegister<3, 240>	TH16; const TH16	H16;
		typedef DefineRegister<3, 241>	TH17; const TH17	H17;
		typedef DefineRegister<3, 242>	TH18; const TH18	H18;
		typedef DefineRegister<3, 243>	TH19; const TH19	H19;
		typedef DefineRegister<3, 244>	TH20; const TH20	H20;
		typedef DefineRegister<3, 245>	TH21; const TH21	H21;
		typedef DefineRegister<3, 246>	TH22; const TH22	H22;
		typedef DefineRegister<3, 247>	TH23; const TH23	H23;
		typedef DefineRegister<3, 248>	TH24; const TH24	H24;
		typedef DefineRegister<3, 249>	TH25; const TH25	H25;
		typedef DefineRegister<3, 250>	TH26; const TH26	H26;
		typedef DefineRegister<3, 251>	TH27; const TH27	H27;
		typedef DefineRegister<3, 252>	TH28; const TH28	H28;
		typedef DefineRegister<3, 253>	TH29; const TH29	H29;
		typedef DefineRegister<3, 254>	TH30; const TH30	H30;
		typedef DefineRegister<3, 255>	TH31; const TH31	H31;

		////----------------------------------------------------
		//// All register group
		////----------------------------------------------------
		//class TRR {
		//public: const U8 regid;
		//	TRR(TG0) :regid(TG0 ::regid){};	TRR(TG1) :regid(TG1 ::regid){};
		//	TRR(TG2) :regid(TG2 ::regid){};	TRR(TG3) :regid(TG3 ::regid){};
		//	TRR(TG4) :regid(TG4 ::regid){};	TRR(TG5) :regid(TG5 ::regid){};
		//	TRR(TG6) :regid(TG6 ::regid){};	TRR(TG7) :regid(TG7 ::regid){};
		//	TRR(TG8) :regid(TG8 ::regid){};	TRR(TG9) :regid(TG9 ::regid){};
		//	TRR(TG10):regid(TG10::regid){};	TRR(TG11):regid(TG11::regid){};
		//	TRR(TG12):regid(TG12::regid){};	TRR(TG13):regid(TG13::regid){};
		//	TRR(TG14):regid(TG14::regid){};	TRR(TG15):regid(TG15::regid){};
		//	TRR(TG16):regid(TG16::regid){};	TRR(TG17):regid(TG17::regid){};
		//	TRR(TG18):regid(TG18::regid){};	TRR(TG19):regid(TG19::regid){};
		//	TRR(TG20):regid(TG20::regid){};	TRR(TG21):regid(TG21::regid){};
		//	TRR(TG22):regid(TG22::regid){};	TRR(TG23):regid(TG23::regid){};
		//	TRR(TG24):regid(TG24::regid){};	TRR(TG25):regid(TG25::regid){};
		//	TRR(TG26):regid(TG26::regid){};	TRR(TG27):regid(TG27::regid){};
		//	TRR(TG28):regid(TG28::regid){};	TRR(TG29):regid(TG29::regid){};
		//	TRR(TG30):regid(TG30::regid){};	TRR(TG31):regid(TG31::regid){};
		//	TRR(TF0) :regid(TF0 ::regid){};	TRR(TF1) :regid(TF1 ::regid){};
		//	TRR(TF2) :regid(TF2 ::regid){};	TRR(TF3) :regid(TF3 ::regid){};
		//	TRR(TF4) :regid(TF4 ::regid){};	TRR(TF5) :regid(TF5 ::regid){};
		//	TRR(TF6) :regid(TF6 ::regid){};	TRR(TF7) :regid(TF7 ::regid){};
		//	TRR(TF8) :regid(TF8 ::regid){};	TRR(TF9) :regid(TF9 ::regid){};
		//	TRR(TF10):regid(TF10::regid){}; TRR(TF11):regid(TF11::regid){};
		//	TRR(TF12):regid(TF12::regid){};	TRR(TF13):regid(TF13::regid){};
		//	TRR(TF14):regid(TF14::regid){};	TRR(TF15):regid(TF15::regid){};
		//	TRR(TF16):regid(TF16::regid){};	TRR(TF17):regid(TF17::regid){};
		//	TRR(TF18):regid(TF18::regid){};	TRR(TF19):regid(TF19::regid){};
		//	TRR(TF20):regid(TF20::regid){};	TRR(TF21):regid(TF21::regid){};
		//	TRR(TF22):regid(TF22::regid){};	TRR(TF23):regid(TF23::regid){};
		//	TRR(TF24):regid(TF24::regid){};	TRR(TF25):regid(TF25::regid){};
		//	TRR(TF26):regid(TF26::regid){};	TRR(TF27):regid(TF27::regid){};
		//	TRR(TF28):regid(TF28::regid){};	TRR(TF29):regid(TF29::regid){};
		//	TRR(TF30):regid(TF30::regid){};	TRR(TF31):regid(TF31::regid){};
		//	TRR(TS0) :regid(TS0 ::regid){};	TRR(TS1) :regid(TS1 ::regid){};
		//	TRR(TS2) :regid(TS2 ::regid){};	TRR(TS3) :regid(TS3 ::regid){};
		//	TRR(TS4) :regid(TS4 ::regid){};	TRR(TS5) :regid(TS5 ::regid){};
		//	TRR(TS6) :regid(TS6 ::regid){};	TRR(TS7) :regid(TS7 ::regid){};
		//	TRR(TS8) :regid(TS8 ::regid){};	TRR(TS9) :regid(TS9 ::regid){};
		//	TRR(TS10):regid(TS10::regid){}; TRR(TS11):regid(TS11::regid){};
		//	TRR(TS12):regid(TS12::regid){}; TRR(TS13):regid(TS13::regid){};
		//	TRR(TS14):regid(TS14::regid){}; TRR(TS15):regid(TS15::regid){};
		//	TRR(TS16):regid(TS16::regid){}; TRR(TS17):regid(TS17::regid){};
		//	TRR(TS18):regid(TS18::regid){}; TRR(TS19):regid(TS19::regid){};
		//	TRR(TS20):regid(TS20::regid){};	TRR(TS21):regid(TS21::regid){};
		//	TRR(TS22):regid(TS22::regid){};	TRR(TS23):regid(TS23::regid){};
		//	TRR(TS24):regid(TS24::regid){};	TRR(TS25):regid(TS25::regid){};
		//	TRR(TS26):regid(TS26::regid){};	TRR(TS27):regid(TS27::regid){};
		//	TRR(TS28):regid(TS28::regid){};	TRR(TS29):regid(TS29::regid){};
		//	TRR(TS30):regid(TS30::regid){};	TRR(TS31):regid(TS31::regid){};
		//	TRR(TH0) :regid(TH0 ::regid){};	TRR(TH1) :regid(TH1 ::regid){};
		//	TRR(TH2) :regid(TH2 ::regid){};	TRR(TH3) :regid(TH3 ::regid){};
		//	TRR(TH4) :regid(TH4 ::regid){};	TRR(TH5) :regid(TH5 ::regid){};
		//	TRR(TH6) :regid(TH6 ::regid){};	TRR(TH7) :regid(TH7 ::regid){};
		//	TRR(TH8) :regid(TH8 ::regid){};	TRR(TH9) :regid(TH9 ::regid){};
		//	TRR(TH10):regid(TH10::regid){};	TRR(TH11):regid(TH11::regid){};
		//	TRR(TH12):regid(TH12::regid){};	TRR(TH13):regid(TH13::regid){};
		//	TRR(TH14):regid(TH14::regid){};	TRR(TH15):regid(TH15::regid){};
		//	TRR(TH16):regid(TH16::regid){};	TRR(TH17):regid(TH17::regid){};
		//	TRR(TH18):regid(TH18::regid){};	TRR(TH19):regid(TH19::regid){};
		//	TRR(TH20):regid(TH20::regid){};	TRR(TH21):regid(TH21::regid){};
		//	TRR(TH22):regid(TH22::regid){};	TRR(TH23):regid(TH23::regid){};
		//	TRR(TH24):regid(TH24::regid){};	TRR(TH25):regid(TH25::regid){};
		//	TRR(TH26):regid(TH26::regid){};	TRR(TH27):regid(TH27::regid){};
		//	TRR(TH28):regid(TH28::regid){};	TRR(TH29):regid(TH29::regid){};
		//	TRR(TH30):regid(TH30::regid){};	TRR(TH31):regid(TH31::regid){};
		//private: TRR& operator=(const TRR&);
		//};

        //----------------------------------------------------
		// Integer register group
		//----------------------------------------------------
		class TRG {
		public: const U8 regid;
			TRG(TG0) :regid(TG0 ::regid){};	TRG(TG1) :regid(TG1 ::regid){};
			TRG(TG2) :regid(TG2 ::regid){};	TRG(TG3) :regid(TG3 ::regid){};
			TRG(TG4) :regid(TG4 ::regid){};	TRG(TG5) :regid(TG5 ::regid){};
			TRG(TG6) :regid(TG6 ::regid){};	TRG(TG7) :regid(TG7 ::regid){};
			TRG(TG8) :regid(TG8 ::regid){};	TRG(TG9) :regid(TG9 ::regid){};
			TRG(TG10):regid(TG10::regid){};	TRG(TG11):regid(TG11::regid){};
			TRG(TG12):regid(TG12::regid){};	TRG(TG13):regid(TG13::regid){};
			TRG(TG14):regid(TG14::regid){};	TRG(TG15):regid(TG15::regid){};
			TRG(TG16):regid(TG16::regid){};	TRG(TG17):regid(TG17::regid){};
			TRG(TG18):regid(TG18::regid){};	TRG(TG19):regid(TG19::regid){};
			TRG(TG20):regid(TG20::regid){};	TRG(TG21):regid(TG21::regid){};
			TRG(TG22):regid(TG22::regid){};	TRG(TG23):regid(TG23::regid){};
			TRG(TG24):regid(TG24::regid){};	TRG(TG25):regid(TG25::regid){};
			TRG(TG26):regid(TG26::regid){};	TRG(TG27):regid(TG27::regid){};
			TRG(TG28):regid(TG28::regid){};	TRG(TG29):regid(TG29::regid){};
			TRG(TG30):regid(TG30::regid){};	TRG(TG31):regid(TG31::regid){};
		private: TRG& operator=(const TRG&);
		};
		
		//----------------------------------------------------
		// Floating register group
		//----------------------------------------------------
		class TRF {
		public: const U8 regid;
			TRF(TF0) :regid(TF0 ::regid){};	TRF(TF1) :regid(TF1 ::regid){};
			TRF(TF2) :regid(TF2 ::regid){};	TRF(TF3) :regid(TF3 ::regid){};
			TRF(TF4) :regid(TF4 ::regid){};	TRF(TF5) :regid(TF5 ::regid){};
			TRF(TF6) :regid(TF6 ::regid){};	TRF(TF7) :regid(TF7 ::regid){};
			TRF(TF8) :regid(TF8 ::regid){};	TRF(TF9) :regid(TF9 ::regid){};
			TRF(TF10):regid(TF10::regid){}; TRF(TF11):regid(TF11::regid){};
			TRF(TF12):regid(TF12::regid){};	TRF(TF13):regid(TF13::regid){};
			TRF(TF14):regid(TF14::regid){};	TRF(TF15):regid(TF15::regid){};
			TRF(TF16):regid(TF16::regid){};	TRF(TF17):regid(TF17::regid){};
			TRF(TF18):regid(TF18::regid){};	TRF(TF19):regid(TF19::regid){};
			TRF(TF20):regid(TF20::regid){};	TRF(TF21):regid(TF21::regid){};
			TRF(TF22):regid(TF22::regid){};	TRF(TF23):regid(TF23::regid){};
			TRF(TF24):regid(TF24::regid){};	TRF(TF25):regid(TF25::regid){};
			TRF(TF26):regid(TF26::regid){};	TRF(TF27):regid(TF27::regid){};
			TRF(TF28):regid(TF28::regid){};	TRF(TF29):regid(TF29::regid){};
			TRF(TF30):regid(TF30::regid){};	TRF(TF31):regid(TF31::regid){};
		private: TRF& operator=(const TRF&);
		};

		//----------------------------------------------------
		// String register group
		//----------------------------------------------------
		class TRS {
		public: const U8 regid;
			TRS(TS0) :regid(TS0 ::regid){};	TRS(TS1) :regid(TS1 ::regid){};
			TRS(TS2) :regid(TS2 ::regid){};	TRS(TS3) :regid(TS3 ::regid){};
			TRS(TS4) :regid(TS4 ::regid){};	TRS(TS5) :regid(TS5 ::regid){};
			TRS(TS6) :regid(TS6 ::regid){};	TRS(TS7) :regid(TS7 ::regid){};
			TRS(TS8) :regid(TS8 ::regid){};	TRS(TS9) :regid(TS9 ::regid){};
			TRS(TS10):regid(TS10::regid){}; TRS(TS11):regid(TS11::regid){};
			TRS(TS12):regid(TS12::regid){}; TRS(TS13):regid(TS13::regid){};
			TRS(TS14):regid(TS14::regid){}; TRS(TS15):regid(TS15::regid){};
			TRS(TS16):regid(TS16::regid){}; TRS(TS17):regid(TS17::regid){};
			TRS(TS18):regid(TS18::regid){}; TRS(TS19):regid(TS19::regid){};
			TRS(TS20):regid(TS20::regid){};	TRS(TS21):regid(TS21::regid){};
			TRS(TS22):regid(TS22::regid){};	TRS(TS23):regid(TS23::regid){};
			TRS(TS24):regid(TS24::regid){};	TRS(TS25):regid(TS25::regid){};
			TRS(TS26):regid(TS26::regid){};	TRS(TS27):regid(TS27::regid){};
			TRS(TS28):regid(TS28::regid){};	TRS(TS29):regid(TS29::regid){};
			TRS(TS30):regid(TS30::regid){};	TRS(TS31):regid(TS31::regid){};
		private: TRS& operator=(const TRS&);
		};

		//----------------------------------------------------
		// Handle register group
		//----------------------------------------------------
		class TRH {
		public: const U8 regid;
			TRH(TH0) :regid(TH0 ::regid){};	TRH(TH1) :regid(TH1 ::regid){};
			TRH(TH2) :regid(TH2 ::regid){};	TRH(TH3) :regid(TH3 ::regid){};
			TRH(TH4) :regid(TH4 ::regid){};	TRH(TH5) :regid(TH5 ::regid){};
			TRH(TH6) :regid(TH6 ::regid){};	TRH(TH7) :regid(TH7 ::regid){};
			TRH(TH8) :regid(TH8 ::regid){};	TRH(TH9) :regid(TH9 ::regid){};
			TRH(TH10):regid(TH10::regid){};	TRH(TH11):regid(TH11::regid){};
			TRH(TH12):regid(TH12::regid){};	TRH(TH13):regid(TH13::regid){};
			TRH(TH14):regid(TH14::regid){};	TRH(TH15):regid(TH15::regid){};
			TRH(TH16):regid(TH16::regid){};	TRH(TH17):regid(TH17::regid){};
			TRH(TH18):regid(TH18::regid){};	TRH(TH19):regid(TH19::regid){};
			TRH(TH20):regid(TH20::regid){};	TRH(TH21):regid(TH21::regid){};
			TRH(TH22):regid(TH22::regid){};	TRH(TH23):regid(TH23::regid){};
			TRH(TH24):regid(TH24::regid){};	TRH(TH25):regid(TH25::regid){};
			TRH(TH26):regid(TH26::regid){};	TRH(TH27):regid(TH27::regid){};
			TRH(TH28):regid(TH28::regid){};	TRH(TH29):regid(TH29::regid){};
			TRH(TH30):regid(TH30::regid){};	TRH(TH31):regid(TH31::regid){};
		private: TRH& operator=(const TRH&);
		};

		//----------------------------------------------------
		// 2-unit integer vector register group
		//----------------------------------------------------
		class TVG2 {
		public: const U8 regid;
			TVG2(TG0) :regid(TG0 ::regid){};	TVG2(TG2) :regid(TG2 ::regid){};
			TVG2(TG4) :regid(TG4 ::regid){};	TVG2(TG6) :regid(TG6 ::regid){};
			TVG2(TG8) :regid(TG8 ::regid){};	TVG2(TG10):regid(TG10::regid){};
			TVG2(TG12):regid(TG12::regid){};	TVG2(TG14):regid(TG14::regid){};
			TVG2(TG16):regid(TG16::regid){};	TVG2(TG18):regid(TG18::regid){};
			TVG2(TG20):regid(TG20::regid){};	TVG2(TG22):regid(TG22::regid){};
			TVG2(TG24):regid(TG24::regid){};	TVG2(TG26):regid(TG26::regid){};
			TVG2(TG28):regid(TG28::regid){};	TVG2(TG30):regid(TG30::regid){};
		private: TVG2& operator=(const TVG2&);
		};

		//----------------------------------------------------
		// 4-unit integer vector register group
		//----------------------------------------------------
		class TVG4 {
		public: const U8 regid;
			TVG4(TG0) :regid(TG0 ::regid){};	TVG4(TG4) :regid(TG4 ::regid){};
			TVG4(TG8) :regid(TG8 ::regid){};	TVG4(TG12):regid(TG12::regid){};
			TVG4(TG16):regid(TG16::regid){};	TVG4(TG20):regid(TG20::regid){};
			TVG4(TG24):regid(TG24::regid){};	TVG4(TG28):regid(TG28::regid){};
		private: TVG4& operator=(const TVG4&);
		};

		//----------------------------------------------------
		// 8-unit integer vector register group
		//----------------------------------------------------
		class TVG8 {
		public: const U8 regid;
			TVG8(TG0) :regid(TG0 ::regid){}; TVG8(TG8) :regid(TG8 ::regid){};
			TVG8(TG16):regid(TG16::regid){}; TVG8(TG24):regid(TG24::regid){};
		private: TVG8& operator=(const TVG8&);
		};

		//----------------------------------------------------
		// 16-unit integer vector register group
		//----------------------------------------------------
		class TVG16 {
		public: const U8 regid;
			TVG16(TG0) :regid(TG0 ::regid){}; TVG16(TG16):regid(TG16::regid){};
		private: TVG16& operator=(const TVG16&);
		};

		//----------------------------------------------------
		// 32-unit integer vector register group
		//----------------------------------------------------
		class TVG32 {
		public: const U8 regid;
			TVG32(TG0):regid(TG0::regid){};
		private: TVG32& operator=(const TVG32&);
		};

		//----------------------------------------------------
		// 2-unit floating vector register group
		//----------------------------------------------------
		class TVF2 {
		public: const U8 regid;
			TVF2(TF0) :regid(TF0 ::regid){};	TVF2(TF2) :regid(TF2 ::regid){};
			TVF2(TF4) :regid(TF4 ::regid){};	TVF2(TF6) :regid(TF6 ::regid){};
			TVF2(TF8) :regid(TF8 ::regid){};	TVF2(TF10):regid(TF10::regid){};
			TVF2(TF12):regid(TF12::regid){};	TVF2(TF14):regid(TF14::regid){};
			TVF2(TF16):regid(TF16::regid){};	TVF2(TF18):regid(TF18::regid){};
			TVF2(TF20):regid(TF20::regid){};	TVF2(TF22):regid(TF22::regid){};
			TVF2(TF24):regid(TF24::regid){};	TVF2(TF26):regid(TF26::regid){};
			TVF2(TF28):regid(TF28::regid){};	TVF2(TF30):regid(TF30::regid){};
		private: TVF2& operator=(const TVF2&);
		};

		//----------------------------------------------------
		// 4-unit floating vector register group
		//----------------------------------------------------
		class TVF4 {
		public: const U8 regid;
			TVF4(TF0) :regid(TF0 ::regid){};	TVF4(TF4) :regid(TF4 ::regid){};
			TVF4(TF8) :regid(TF8 ::regid){};	TVF4(TF12):regid(TF12::regid){};
			TVF4(TF16):regid(TF16::regid){};	TVF4(TF20):regid(TF20::regid){};
			TVF4(TF24):regid(TF24::regid){};	TVF4(TF28):regid(TF28::regid){};
		private: TVF4& operator=(const TVF4&);
		};

		//----------------------------------------------------
		// 8-unit floating vector register group
		//----------------------------------------------------
		class TVF8 {
		public: const U8 regid;
			TVF8(TF0) :regid(TF0 ::regid){}; TVF8(TF8) :regid(TF8 ::regid){};
			TVF8(TF16):regid(TF16::regid){}; TVF8(TF24):regid(TF24::regid){};
		private: TVF8& operator=(const TVF8&);
		};

		//----------------------------------------------------
		// 16-unit floating vector register group
		//----------------------------------------------------
		class TVF16 {
		public: const U8 regid;
			TVF16(TF0):regid(TF0 ::regid){}; TVF16(TF16):regid(TF16::regid){};
		private: TVF16& operator=(const TVF16&);
		};

		//----------------------------------------------------
		// 32-unit floating vector register group
		//----------------------------------------------------
		class TVF32 {
		public: const U8 regid;
			TVF32(TF0):regid(TF0::regid){};
		private: TVF32& operator=(const TVF32&);
		};
	}

	///////////////////////////////////////////////////////////////
	// Code Name
	///////////////////////////////////////////////////////////////
	namespace Codename
	{
		enum Code
		{
			noop = 0,
			init,
			halt,

			vcall,
			rcall,
			// assignment:
			//rmov a, b
			rmov,	// 
			//imov a, x
			imov,

			//load a. m
			load,
			//save m, a
			save,
			//allo m, x
			allo,
			//free m
			free,

			//// math:
			//radd a, b
			radd,
			//iadd a, x
			iadd,
			//vadd a, b
			vadd,

			//rdec a, b
			rdec,
			//idec a, x
			idec,
			//vdec a, b
			vdec,

			//rmul a, b
			rmul,
			//imul a, x
			imul,
			//vmul a, b
			vmul,

			//rdiv a, b
			rdiv,
			//idiv a, x
			idiv,
			//vdiv a, b
			vdiv,

			//rsum a, b, c
			rsum,
			//isum a, b, x
			isum,
			//vsum a, x, y
			vsum,

			//swap a, b
			swap,
			//rshl a, b
			rshl,
			//rshr a, b
			rshr,
			//ishl a, x
			ishl,
			//ishr a, x
			ishr,

			//rrol a, b
			rrol,
			//rror a, b
			rror,
			//irol a, x
			irol,
			//iror a, x
			iror,

			//scat sa, sb	=> sadd
			sadd,
			//srev sa, sb
			srev,
			//sfnd a, sa, sb, b
			sfnd,
			//slen a, s
			slen,

			//sist sa, a, x
			//srst sa, a, b
			//ssst sa, a, sb

			//ssub sa, sb, a, b
			ssub,
			//srol s, a
			srol,
			//sror s, a
			sror,
			//sirl s, x
			sirl,
			//sirr s. x
			sirr,
			//srch a, s, b
			srch,
			//sich a, s, x
			sich,

			//ror a, b
			ror,
			//ior a, x
			ior,

			//rnot a
			rnot,

			//rxor a, b
			rxor,
			//ixor a, x
			ixor,

			//rand a, x
			rand,
			//iand a, x
			iand,

			//nois a		// get random number
			nois,

			//rdtk a		// read tick
			rdtk,

			//rcmp a, b	// compare
			rcmp,
			//icmp a, x	// compare
			icmp,

			rdtm,	//	Get time
			//sttm a	// 	Set time
			sttm,

			vmid,	// Get machine id
			guid,	// Get global unique id

			floor
			
		/*	loadoffset	reg, S/H
			loadoffset_x1
			loadoffset_x2
			loadoffset_x4

			initzero	G/F/S/H
			loadunit_1	G/F, val
			loadunit_2
			loadunit_3
			loadunit_4
			loadunit_5
			loadunit_6
			loadunit_7
			loadunit_8
			loadpack_x1	S/H, val
			loadpack_x2	
			loadpack_x4	

			pushi_g
			pushi_f
			pushg
			pushf
			pushr	reg


			add
			sub
			div
			mul
			pow
			log
			sin
			cos
			tan
			sum
			ave
		*/
		};
	}


	///////////////////////////////////////////////////////////////
	//	Cell Name
	///////////////////////////////////////////////////////////////
	namespace Cellname
	{
		enum Cell
		{
			GCELL		= 0,		//IntegerObject
			FCELL		= 1,		//FloatingObject
			G2CELL		= 2,		//IntegerObject[2]
			F2CELL		= 3,		//FloatingObject[2]
			G4CELL		= 4,		//IntegerObject[4]
			F4CELL		= 5,		//FloatingObject[4]
			G8CELL		= 6,		//IntegerObject[8]
			F8CELL		= 7,		//FloatingObject[8]
			G16CELL		= 8,		//IntegerObject[16]
			F16CELL		= 9,		//FloatingObject[16]
			G32CELL		= 10,		//IntegerObject[32]
			F32CELL		= 11,		//FloatingObject[32]
			G64CELL		= 12,		//IntegerObject[64]
			F64CELL		= 13,		//FloatingObject[64]
			G128CELL	= 14,		//IntegerObject[128]
			F128CELL	= 15,		//FloatingObject[128]
			
			RGCELL		= 16,		//Cellname
			RFCELL		= 17,		//Cellname
			RG2CELL		= 18,		//Cellname
			RF2CELL		= 19,		//Cellname
			RG4CELL		= 20,		//Cellname
			RF4CELL		= 21,		//Cellname
			RG8CELL		= 22,		//Cellname
			RF8CELL		= 23,		//Cellname
			RG16CELL	= 24,		//Cellname
			RF16CELL	= 25,		//Cellname
			RG32CELL	= 26,		//Cellname
			RF32CELL	= 27,		//Cellname
			RG64CELL	= 28,		//Cellname
			RF64CELL	= 29,		//Cellname
			RG128CELL	= 30,		//Cellname
			RF128CELL	= 31,		//Cellname
			
			HCELL		= 64,		//HandleObject
			SCELL		= 65,		//StringObject
			RCELL		= 66,
			RHCELL		= 67,		//Cellname
			RSCELL		= 68,		//Cellname

			B1JBCELL	= 0xE1,		//jumper block
			B2JBCELL	= 0xE2,		//jumper block
			B4JBCELL	= 0xE3,		//jumper block
			B8JBCELL	= 0xE4,		//jumper block
			MBJBCELL	= 0xE5,		//jumper for marker block
			JBJBCELL	= 0xE6,		//jumper for jumper block

			VOIDCELL	= 0xD1,		//-
			INVALIDCELL = 0xFF		//-
		};
	};
	


	//----------------------------------------------------
	// TraitsOfCell
	//----------------------------------------------------
	template<unsigned int> struct TraitsOfCell;

	template<> struct TraitsOfCell<Cellname::GCELL>		{ typedef IntegerObject type; enum { size = sizeof(type) };  };
	template<> struct TraitsOfCell<Cellname::FCELL>		{ typedef FloatingObject type; enum { size = sizeof(type) };  };

	template<> struct TraitsOfCell<Cellname::G2CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::GCELL>::size * 2 };
	
		typedef struct {
			U8				cellname;
			IntegerObject	integers[2];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::F2CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::FCELL>::size * 2 };
		
		typedef struct {
			U8				cellname;
			FloatingObject	Floatings[2];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::G4CELL>
	{
		enum { size = TraitsOfCell<Cellname::GCELL>::size * 4 };

		typedef struct {
			U8				cellname;
			IntegerObject	integers[4];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::F4CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::FCELL>::size * 4 };

		typedef struct {
			U8				cellname;
			FloatingObject	Floatings[4];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::G8CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::GCELL>::size * 8 };

		typedef struct {
			U8				cellname;
			IntegerObject	integers[8];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::F8CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::FCELL>::size * 8 };

		typedef struct {
			U8				cellname;
			FloatingObject	Floatings[8];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::G16CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::GCELL>::size * 16 };

		typedef struct {
			U8				cellname;
			IntegerObject	integers[16];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::F16CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::FCELL>::size * 16 };
	
		typedef struct {
			U8				cellname;
			FloatingObject	Floatings[16];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::G32CELL>
	{
		enum { size = TraitsOfCell<Cellname::GCELL>::size * 32 };

		typedef struct {
			U8				cellname;
			IntegerObject	integers[32];
		} CellFrame;
	};	

	template<> struct TraitsOfCell<Cellname::F32CELL>
	{ 
		enum { size = TraitsOfCell<Cellname::FCELL>::size * 32 };

		typedef struct {
			U8				cellname;
			FloatingObject	Floatings[32];
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::RCELL>
	{ 
		enum { size = sizeof(U8) };

		typedef struct {
			U8				cellname;
			U8				regid;
		} CellFrame;
	};

	template<> struct TraitsOfCell<Cellname::SCELL>
	{ 
		enum { size = TraitsOfCell<Cellname::RCELL>::size };
	
		typedef struct {
			U8				cellname;
			U8				regid;
		} CellFrame;
	};


	template<> struct TraitsOfCell<Cellname::HCELL>
	{ 
		enum { size = TraitsOfCell<Cellname::RCELL>::size };

		typedef struct {
			U8				cellname;
			U8				regid;
		} CellFrame;
	};

	
	//----------------------------------------------------
	// GetCellSize
	//----------------------------------------------------
/*
	inline unsigned int GetCellSize(const Cellname::Cell& cell)
	{
		switch(cell) {	
		case Cellname::RCELL:	return TraitsOfCell<Cellname::RCELL  >::size;
		case Cellname::GCELL:   return TraitsOfCell<Cellname::GCELL  >::size;
		case Cellname::FCELL:   return TraitsOfCell<Cellname::FCELL  >::size;
		case Cellname::G2CELL:  return TraitsOfCell<Cellname::G2CELL >::size;
		case Cellname::F2CELL:  return TraitsOfCell<Cellname::F2CELL >::size;
		case Cellname::G4CELL:  return TraitsOfCell<Cellname::G4CELL >::size;
		case Cellname::F4CELL:  return TraitsOfCell<Cellname::F4CELL >::size;
		case Cellname::G8CELL:  return TraitsOfCell<Cellname::G8CELL >::size;
		case Cellname::F8CELL:  return TraitsOfCell<Cellname::F8CELL >::size;
		case Cellname::G16CELL: return TraitsOfCell<Cellname::G16CELL>::size;
		case Cellname::F16CELL: return TraitsOfCell<Cellname::F16CELL>::size;
		case Cellname::G32CELL: return TraitsOfCell<Cellname::G32CELL>::size;
		case Cellname::F32CELL: return TraitsOfCell<Cellname::F32CELL>::size;
		case Cellname::SCELL:	return TraitsOfCell<Cellname::SCELL  >::size;
		case Cellname::HCELL:	return TraitsOfCell<Cellname::HCELL  >::size;
		}
		return TraitsOfCell<Cellname::INVALIDCELL>::size;	//throw();
	}
*/

	
}

#endif	//ifndef GMACHINE_HEADER_GPROFILE_H
